BSR MODE IN 8255 PDF

Mode selection bits, D2, D5, D6 are all 0 for mode 0 operation. The two halves of port C can be either used together as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C are independent, they may be used such that one-half is initialized as an input port while the other half is initialized as an output port. Input ports are buffered, not latched.

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Bit set reset BSR mode — This mode is used to set or reset the bits of port C only, and selected when the most significant bit D7 in the control register is 0. Control Register is as follows: This mode affects only one bit of port C at a time because, as user set the bit, it remains set until and unless user changes it.

User needs to load the bit pattern in control register to change the bit. The outputs are latched but the inputs are not latched. It has interrupt handling capability. The outputs as well as inputs are latched. Before actual data transfer there is transmission of signal to match speed of CPU and printer.

Example: When CPU wants to send data to slow peripheral device like printer, it will send handshaking signal to printer to tell whether it is ready or not to transfer the data. When printer will be ready it will send one acknowledgement to CPU then there will be transfer of data through data bus.

D4 is used to tell whether port A is taking input or displaying the result. If it is 1 then it is taking input otherwise displaying output. D3 is used to tell whether port C higher bits is taking input or displaying the result. D2 tells the mode of port B. If it is 0 then port B is in m0 mode otherwise in m1 mode. D1 is used to tell whether port B is taking input or displaying the result. D0 is used to tell whether port C lower bits is taking input or displaying the result.

When microprocessor is reset, it will clear the control word register contents, setting all the ports to input mode.

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